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VIA Technologies, Inc.
Preliminary VT86C100A
VT86C100A
PCI FAST ETHERNET CONTROLLER
DATA SHEET
(Preliminary)
DATE : Aug 31, 1997
VIA TECHNOLOGIES, INC.
VIA Technologies, Inc.
Preliminary VT86C100A
PRELIMINARY RELEASE Please contact Via Technologies for the latest documentation.
Copyright Notice:
Copyright (c) 1995, Via Technologies Incorporated. Printed in Taiwan. ALL RIGHTS RESERVED. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of Via Technologies Incorporated. The VT86C100A may only be used to identify products of Via Technologies. All trademarks are the properties of their respective owners.
Disclaimer Notice:
No license is granted, implied or otherwise, under any patent or patent rights of Via Technologies. Via Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable to the publication date of this document. However, Via Technologies assumes no responsibility for any errors in this document. Furthermore, Via Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change.
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Preliminary VT86C100A
VT86C100A PCI FAST ETHERNET CONTROLLER FEATURES
* Single chip Fast Ethernet controller for PCI bus interface -- compliant to PCI v2.1 with optional delay transaction and sub-vendor, sub-system- ID -- Provides a direct connection to PCI bus -- Supports two network ports : 10/100 M MII interface * High performance PCI mastering structure -- VIA self-define 128 bytes memory I/O or register I/O based command and status register -- Software oriented chain structure description to minimize hardware complexity -- Include on chip bus master DMA with programmable burst length for low CPU utilization -- Dynamic transmit packet auto queuing for back auto queuing for bac for back to back transmissin -- Programmable activity polling intervals for description DMA -- Programmable DMA arbitration priority to minimize overflow under flow condition -- Support early receive and early transmit interrupt for software parallel processing -- Interrupt controllable by receive/transmit descriptor list for saving interrupt service time * Provides standard 100-M bits MII interface -- Support 100Base-TX with CAT5 UTP, STP and fiber cables -- Support 100Base-T4 with CAT3, CAT4, CAT 5 UTP, STP * 10/100Mhz full duplex, half duplex operation * Contains two deeper 2K bytes FIFO for receive and transmit controller both supports bursts of up to full Ethernet length -- Programmable receive and transmit FIFO threshold control for optimize PCI throughput * Flexible dynamically load EEPROM algorithm. -- Load after power-up -- Dynamic auto reload -- Embedded programming for configure modification -- Dynamic direct programming for manufacturing * Support physical, Broadcast, Multicast address filtering using hashing function * Support Magic packet and wake on address filtering * Support external Bootrom up to 64K bytes no external address latch * Software controllable power down feature * Single +5V supply, 0.5um standard CMOS technology * 128 pin PQFP package
VIA Technologies, Inc.
Preliminary VT86C100A
PCI v2.1
Boot ROM
Config. EEPROM
_MSRD, _MSWR, EECS AD[31:0] PCICLK PCIRST# INTA# CBE#[3:0] IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# PAR
Configuration Registers & EEPROM Control
Tally Counters
PCI Bus Interface Unit
Master Registers State & Machine Buffer & Mgmt.
RxFIFO 2K bytes
TxFIFO 2K bytes
10/100M MAC Tx/Rx Protocol State
MII
TXD[3:0], RXD[3:0], TX_EN TX_ER, RX_ER TX_CLK, RX_CLK RX_DV, CRS, COL MDIO
PCI CFG
Figure 1: Application Diagram
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Preliminary VT86C100A
PIN DIAGRAM
MRXDV MRXC MERR MTXC VSS VDD MTXE MTXD0 MTXD1 MTXD2 MTXD3 MCOL MCRS TST VSS VDD NC2 GPIO1/AUXPME MA15 MA14 MA13 MA12 MA11 MA10 MA9 VSS VDD RAMVSS RAMVDD MA8 MA7 MA6 MA5 MA4 MA3 MA2 VSS VDD 1 0 2 1 0 0 9 5 9 0 8 5 8 0 7 5 7 0 6 5 64 MA1 MA0 NC NC MD7 MD6 MD5 VSS VDD MD4 MD3 MD2 MD1 MD0 BPRD# ECS VSS VDD AD0 AD1 AD2 AD3 AD4 VSS AD5 AD6
MRXD0 MRXD1 MRXD2 MRXD3 VSS VDD MDC MDIO HDRST M10TEN INTA# PCIRST# PCICLK VSS VDD GNT# REQ# PME# AD31 AD30 AD29 AD28 VDD VSS AD27 AD26
103 105
60 110 55
115
VT86C100A
50
120 45 125 128 1 5 1 0 1 5 2 0 2 5 3 0 3 5 3 8 39
AD25 AD24 CEB3# IDSEL AD23 VSS AD22 AD21 AD20 VDD AD19 AD18 AD17 AD16 VSS CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP# VDD PERR# VSS PAR CBE1# AD15 AD14 AD13 AD12 AD11 AD10 VSS VDD AD9 AD8 CBE0# AD7
VIA Technologies, Inc.
Preliminary VT86C100A
PIN DESCRIPTIONS
No.
124,127128,12,5,79,1114,2732,3536,38,3940,42-46 115 113 114
Name
Type
I/O
Description
Address/Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. The address phase is the clock cycle in which FRAME# is asserted. Write data is stable and valid when IRDYB is asserted and read data is stable and valid when TRDYB is asserted.
PCI Bus Interface 121AD31-0
PCICLK INTA# PCIRST#
I OD I
3,16,26,37
CBE#[3:0]
I
4 17
IDSEL FRAME#
I I/O
18
IRDY#
I/O
19
TRDY#
I/O
20
DEVSEL#
I/O
21
STOP#
I/O
PCICLK provides timing for all transactions on PCI and is an input pin to every PCI device. INTA# is an asynchronous signal which is used to request an interrupt When PCIRST# is asserted low, the VT86C100A chip performs an internal system hardware reset. PCIRST# may be asynchronous to CLK when asserted or deasserted. It is recommended that the deassertion be synchronous to guarantee clean and bounce free edge. Bus Command/Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, CBE3-0B define the Bus Command. Burring the data phase, CBE3-0B are used as Byte Enables. The Byte Enables define which physical byte lanes carry meaningful data. CBE0B applies to byte 0 and CBE3B applies to byte 3. Used as a chip select during PCI configuration cycle. Cycle Frame is driven by the current master to indicate the beginning and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is deasserted, the transaction is in the final data phase. Initiator Ready indicates the initiating agent's ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock when both IRDY# and TRDY# are asserted. During a write, IRDY# indicates that valid data is present on AD31-0. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted simultaneously. Target Ready indicates the target's agent's ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock when both IRDY# and TRDY# are asserted. During a read, TRDY# indicates that valid data is present on AD31-0. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted simultaneously. Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. VT86C100A drives STOP# to disconnect further traction.
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Preliminary VT86C100A
25
PAR
T/S
118 119 23 120 111
GNT# REQ# PERR# PME# HDRST
I O I/O O O
Parity is even parity across AD31-0 and CBE3-0B. PAR is stable and valid one clock after the address phase. For data phases PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. Bus grant asserts to indicate to the VT86C100A that access to the bus is granted. Bus request is asserted by the bus master indicate to the bus arbiter that it wants to use the bus. Parity error asserts when a data parity error is detected Power management event interrupt When PCIRST# is asserted low, the VT86C100A chip performs an internal system hardware reset. Then HDRST is asserted high for external device reset signal like PHY device.
Network Interface 91 MCOL 90 MCRS 92-95 MTXD[3-0]
Collision detect when the external PHY device Carrier sense is asserted by the external PHY when the media is active MII 4 parallel transmit data lines. This data be synchronized to assertion by the MTXC signal 96 MTXEN O Transmit enable signals that the transmit is active in the MII port to an external PHY device 99 MTXC I MII transmit clock supports the 25mhz or 2.5mhz transmit clock supplied by the external PMD device. This clock should always be active. 100 MERR I MII receive error asserts when a data decoding error is detected by external PHY device. 101 MRXC I MII receive clock supports the 25mhz or 2.5mhz clock. This clock is recovered by the PHY. 102 MRXDV I MII data valid 103-106 MRXD[0-3] I Four parallel receive data lines. This data be driven from external PHY be synchronized with MRXC signal. 109 MDC O MII management data clock be soured by VT86C100A MDC bit (MIIR:0) to the external PHY devices as timing reference for the MDIO signal. 110 MDIO I/O MII management data input/output, read from MDI bit (MIIR:1) or written from MDO bit (MIIR:2) 112 GPIO I/O GPIO External Memory Support & General purpose I/O support 49 EECS O EEPROM Chip Select: Chip select signal for the external EEPROM when a EEPROM is used to provide the configuration data and Ethernet Address. A 100K pull-up resistor is connected. 50 BPRD# O Boot PROM Read: Read the Boot ROM on the memory support data bus. 51 MD0/ I/O Bootrom data 0 EEDO Serial ROM Data output 52 MD1/ O/O Bootrom data 1 EEDI Serial ROM Data input 53 MD2/ EECLK O/O Bootrom data 2 Serial ROM Clock signal 54-55,58MD3-7 I/O Bootrom Data [3-7] : 60
I I O
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Preliminary VT86C100A
63-64,6773,7884 85 112
MA0-MA15
O
Bootrom address line [0-15]
GPIO1/AUXP ME GPIO2/LKC
IO IO
General purpose input and output 1 : usually as Magic key interrupt line General purpose input and output 2, this pin usually as link change status from external PHY device. Positive 5V Supply: Supply power to Internal digital logic, Digital I/O pads, and TD, TX pads. Double bonding may be required. Negative Supply: digital ground. Multiple bonding pads are required to separate core and I/O pads ground.
Power Supply & Ground 10,22,34,47, VDD, VDDA
56,65,76, 87,97,108 ,117,125 6,15,24,33, 41,48,57 ,66,75,7 7,88,98, 107,116, 126
P
VSS, VSSA
G
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Preliminary VT86C100A
FUNCTIONAL DESCRIPTIONS 1. GENERAL DESCRIPTION
The VT86C100A Rhine ACPI PCI bus master 100 M FAST Ethernet controller is CMOS VLSI designed for easy implementation of CSMA/CD IEEE 802.3u 100M local area networks. Significant features include: twisted-pair interface, PCI Plug&Play compatibility, 32 bit bus mastering, powerful buffer management and Early Interrupt Receive/Transmit. The VT86C100A integrates the entire bus interface of PCI systems. Setting hardware jumpers or software configures the VT86C100A bus interface. The VT86C100A also complies with PCI specification v2.1.. The VT86C100A supports the Media Independent Interface (MII) network interface.
1.1 FIFO AND CONTROL LOGIC
The VT86C100A incorporates two independent 2K bytes deeper FIFO for transmit or receive data from system interface or to the network interface, providing temporary storage of data, free host system from the real-time demands on network. The VT86C100A enhanced the FIFO management logic to handle received data packets up to four packets before transfer to system data buffer. This ability reduce the packets losing due to PCI bus mastering abrition latency.
2. NETWORK INTERFACE
The VT86C100A Rhine ACPI support one MII interface
2.1 MII Interface
The MII interface is an IEEE 802.3 compliant interface that provides a simple and easy interconnection between the MAC layer and PHY device. This interface has support the following characteristics : * Support both 10M and 100M data rate. * Contains data and synchronous clock * 4-bit independent receive and transmit data. * Uses TTL signal levels and compatibles with common CMOS processes.
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Preliminary VT86C100A
3.
EEPROM Interface and Programming
VT86C100A uses an 93C46 to store configuration data and Ethernet address. 3.1. EEPROM Contents D15 3FH . . . . . . 10H 0FH 0EH 0DH 0CH 0BH 0AH 09H 08H 07H 06H 05H 04H 03H 02H 01H 00H Reserved for 93C46 . . . . . . . 73H CFG_D CFG_B BCR1 MAX_LAT Reserved KEY5 KEY3 KEY1 Reserved SUBVID1 SUBSID1 Reserved Ethernet Address 5 Ethernet Address 3 Ethernet Address 1 Reserved for 93C46 . . . . . . . 73H CFG_C CFG_A BCR0 MIN_GNT Reserved KEY5 KEY2 KEY0 Reserved SUBVID0 SUBSID0 Reserved Ethernet Address 4 Ethernet Address 2 Ethernet Address 0 D0
Note 1. The word on location 03H is optional to user's application requirement. Note 2. Programming 73H into the upper address is required to protect the Ethernet address from being destroyed accidentally Note 3. The word on location 04H, 05H is sub-System ID, sub-Vendor ID in PCI specification 2.1.
3.2. DIRECT PROGRAMMING OF EEPROM
The VT86C100A features a easy way to program external EEPROM in-situ. When the RESET is active and if the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current EEPROM has not been programmed yet. This will allow the VT86C100A to enter Direct Programming mode if EELOAD is also set. In this mode the user can directly control the EEPROM interface signals by writing to the ECSR Port and the value on the EECS, ESK and EDI bits will be driven onto the EECS, SK(MD2), and DI(MD1) outputs respectively. These outputs will be latched so the user can generate a clock on SK by repetitively writing 1 then 0 to the appropriate bit. This can be used to generate the EEPROM signals as per the 93C46 data sheet. To read the EEPROM data, users have to generate EEPROM interface signals into EECS, DI and SK as described above and in the mean time read the data from DO(MD0) input via pin SD0. Reading Data Transfer Port during programming will not affect the latched data on EECS, SK, and DI outputs. When the
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Preliminary VT86C100A
EEPROM has been programmed and verified (remember to program the upper byte of 0EH & 0FH with 73H), the user must give VT86C100A a power-on reset to return to normal operation and to read in the new data. The Direct Programming mode is mainly used for production to program every bit of the EEPROM. Once the upper byte of 0EH has been programmed with 073H and a power-on reset has been performed, there is no way to change the contents of EEPROM except Configuration Registers A, B, and C, which will be discussed in the following paragraph. For more information, refer to EECSR.
3.3. EMBEDDED PROGRAMMING OF EEPROM
If the upper byte of 0FH of EEPROM has been programmed to 073H when VT86C100A is loading the EEPROM data during power-on reset, the EEPR bit of Signature Register will be set to prohibit the Direct Programming mode. However, the user can still program the configuration registers A, B, and C using the Embedded Programming mode by following the routine specified in the pseudo code below. This operation will work regardless of the value of EECONFIG. The setting of the EELOAD bit of Configuration Register B starts the EEPROM write process. Care should be taken not to accidentally modify the POL and GDLNK bits because these two bits return the value indifferent from the setting. This programming process is ended when the EELOAD bit goes to zero. EEPROM_EMB_PROG ( ) // defined constant: CONFIG_B, EELOAD // declared register: value, config_for_A, config_for_B, config_for_C // declared function: DISABLE_INTERRUPTS, ENABLE_INTERRUPTS, READ, WRITE, WAIT DISABLE_INTERRUPTS ( ); value = READ (CONFIG_B); value = value | EELOAD; WRITE (CONFIG_B, value); READ (CONFIG_B); WRITE (CONFIG_B, config_for_A); WRITE (CONFIG_B, config_for_B); WRITE (CONFIG_B, config_for_C); while (value || EELOAD) { value = READ (CONFIG_B); WAIT ( ); } ENABLE_INTERRUPTS ( );
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Preliminary VT86C100A
4. PCI Configuration Space
Device ID ( 6100 ) STATUS (DEVS1, DEVS0 ) = ( 1 , 0 ) CLASS CODE ( 02_00_00 ) Header type
Vendor ID 00 h ( 1106 ) COMMAND 04 h ( MMSPACE, IOSPACE) Revision ID 08 h ( 04 ) Cache Line 0c h ( R/W ) 000 0 0 0 1 10 h CSR IO MAP SPACE 000 0000 14 h 2c h
BIST ( 00 )
Latency Timer
( 00 ) ( R/W ) CSR Memory Map Base Addr
Sub-System ID EXP ROM BASE [ 31: 15 ] ROM14
Sub-Vendor ID 0000_0000_00000 EN 30 h
Reserved Max_LAT ( 00 ) Min_GNT ( 00 ) Reserved MODE2 INT PIN ( 01 )
Reserved INTLINE 3c h INTL [7:0] Reserved MODE0
MODE3
FIFOTST
50H
5. MAGIC KEY FILTERING AND WAKE ON MAGIC KEY
The VT86C100A provides an one level power down mode. The BIOS or Network OS device driver can configure Register A to diagnostic mode then set the Power-on bit of the diagnostic port to "on." When the VT86C100A is in Power down mode, all power to the PCI interface is cut off and the chip clock is stopped. Other registers are read only. Only the diagnostic port is read/writeable. The VT86C100A can store one "Magic Key" (6 bytes Ethernet address) as external trigger event. When VT86C100A received one Magic Key address packet, the PME# or GPIO1 will be generated to system. These signal can be asserted to ATX power PS-ON (refere to ATX specification v2.01) or mother board wake up interrupt line like ring-in.
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Preliminary VT86C100A
6. BUFFER MANAGEMENT & HOST COMMUNICATION
The VT86C100A provides an simply and effective buffer management and host communication method through the PCI Bus mastering : There are two descriptor lists, one for receive and one for transmit. The base of these two list are pointed into the CRDA (18h) and CTDA (1ch) registers. The descriptor list reside in the host physical memory address space with double word boundary. And each descriptor lists just point to one single buffer, but a data buffer consists of either an entire frame or part of a frame. Data chain can be enabled or disabled by DES1 C bit. Data buffer also reside in host physical memory double word boundary space. The device driver can make the last descriptors next link be point to first descriptor address, become a ring buffer structure.
Buffer 1 Descriptor 0
Buffer 1
Descriptor 1
Next Descriptor
Figure 6-1 VT86C100A Buffer Management : Chain buffer Structure 6.1 DESCRIPTOR RING AND CHAIN STRUCTURE 6.1.1 RECEIVE DESCRIPTORS
Figure 6-2 shows the receive descriptor format : Providing single buffer, one byte-count buffers, and next descriptor address. And Chain bit control span multiple data buffers data chain to be compatible various types of memory management schemes..
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Preliminary VT86C100A
31 RDES0 RDES1 RDES2 RDES3
O0000
23
FLNG[10:0]
15
RSR1 RSR0
RLNG[10:0]
Reserve
Reserve C 0000 Rx Data Buffer Start Address Next Descriptor Address
THE RECEIVE DESCRIPTOR FORMAT
FIGURE 6-2
:
6.1.2. RECEIVE DESCRIPTOR 0 (RDES0)
RDES0 contain the received frame status, the frame length and the descriptor ownership information.
Owner : This bit control by driver, 1 to identify this descriptor own by VT86C100A controller, 0 means this descriptor be a free descriptor; Driver must set this bit be zero when initialed. Extend Frame Length : Extend byte count for no-normal size Ethernet frame Frame Length : Received frame length, Received OK : The VT86C100A received a good packet from network. Multicast Address Received : VT86C100A MAC received multicast address packet Boardcast Address Received : VT86C100A MAC received boardcast address packet Physical Address Received : Physical address received CHAIN : means of chain buffer, Start of Packet : In descriptor ring structure, STP=EDP=1 single buffer descriptor, or chained buffer structure be follows : STP EDP Description 1 1 Single buffer descriptor 1 0 First buffer descriptor, further buffer chained 0 1 Chained buffer packet end 0 0 X End of Packet : End of Packet buffer Receive Status Register 0 : Buffer Error : Receive Buffer Error System bus error : Runt Packet Received : Long Packet Received : FIFO Overflow : Frame Align Error : CRC Error : received frame CRC checksum error Receive Error : this bit be set by CRC error or frame alignmnet error or FIFO overflow or System bus error.
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Preliminary VT86C100A
6.1.3. RECEIVE DESCRIPTOR 1 (RDES1)
RDES1 contain the interrupt control enable, the chained frame identical and the receive buffer fragment size information.
Interrupt Control : This bit support for interrupt PACEing , set 1 mean the VT86C100A received this descriptor will generate the interrupt. Chain : Chain buffer , this bit be set to 1 means there are chained buffer in next descriptor Extend Fragment of Frame Length : must be zero now. Rx buffer Size : Receive buffer size for this descriptor, the total byte count of whole frame will be stored in last descriptors
6.2.1. TRANSMIT DESCRIPTORS 31 RDES0 RDES1 RDES2 RDES3
O
23
Reserve
15
TSR1 TSR0
TLNG[10:0]
Reserve
TCR C 0000 Tx Data Buffer Start Address Next Descriptor Address
THE TRANSMIT DESCRIPTOR FORMAT
FIGURE 6-3
6.2.2. TRANSMIT DESCRIPTOR 0 (TDES0)
DES0 contain the received frame status, the frame length and the descriptor ownership information.
Owner : This bit control by driver, 1 to identify this descriptor own by VT86C100A controller, 0 means this descriptor be a descriptor waiting for transmit; Driver must set this bit be zero when initialed.
14
JAB
Transmit Status Register 1 Transmit OK : This bit be 1 for transmission error, the transmit include following - internal FIFO under-flow - excessive collision (ABT) - late collision (OWC) - carrier sense lost (CRS) Jabber : This bit will set high if Jabber condition happens. Writing to this bit has no effect System Error : VT86C100A MAC experience error master abort, target abort, parity error.
12 11
Reserve Reserve
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Preliminary VT86C100A
10 9 8 7-0
CRS OWC ABT TSR0
Carrier Sense lost bit is set when the carrier is lost during the transmission of a packet.
Late Collisions : This bit is set when late collision occurred. Transmit Abort : transmit module abort after excessive collision. Transmit Status Register 0 CD heartbeat : this bit only effective in 10Base-T mode. When set, this bit indicates a heartbeat collision check failure. Collision retry count : this 4-bits counter indicates the number of collisions that occurred FIFO under-flow : this bit set indicates that the transmitter aborted by transmit FIFO encountered an empty while transmitting a frame. Deferred: When set, indicates that the VT86C100A had to defer while ready to transmit a frame because carrier was asserted.
6.2.3. TRANSMIT DESCRIPTOR 1 (TDES1)
DES1 contain the transmit status, the frame length and the descriptor ownership information.
Transmit Configure Register Interrupt Control : This bit support for interrupt PACEing , set 1 mean the VT86C100A received this descriptor will generate the interrupt. End of Packet : End of Packet buffer Start of Packet : In descriptor ring structure, STP=EDP=1 single buffer descriptor, or chained buffer structure be follows : STP EDP Description 1 1 Single buffer descriptor 1 0 First buffer descriptor, further buffer chained 0 1 Chained buffer packet end 0 0 X
CRC disable : The VT86C100A transmitter will disable generated the CRC when this set 1. Chain : Chain buffer Extend Fragment of Frame Length : must be zero now. Transmit buffer size : the fragment of frame buffer size
6.3 Buffer Structure and Interrupt Control
data consists of an entire frame or part of a frame, but it cannot exceed a single Ethernet frame size. Buffers contain only data; All buffer status is maintained in the descriptor . Data chaining can be enable or disable by Chain bit in DES1[15]. The interrupt control also can be enable or disable by DES1[23]
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Preliminary VT86C100A
6.3.1 Multiple Chained buffer structure
The VT86C100A can support multiple chain buffer for direct map to OSs data buffer. The VT86C100A bus mastering module will direct move the data from network to the OSs data buffer or direct transmit the data in OSs buffer onto network not necessary move to a temperate data buffer. But the data buffer must be double word aligned. In this multiple chained buffer structure, the first data buffer descriptor Chain
Simple Ring Buffer Structure Multiple Buffer Frame 0 F0 C F0 C F0 F0
0
F1
0
F2
0
C=DES1[15] Figure 6 : Ring buffer and multiple buffer structure
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Preliminary VT86C100A
6.3.2 Interrupt Control
The VT86C100A can controllable the receive descriptors and transmit descriptor for what the interrupt occurred. The IC bit (DES1[23]) be set 1, the receive or transmit interrupt will be generate the interrupt no matter the frame been complete received or transmitted. This feature will enable the OS pre-fetch the frame header or saving the interrupt service overload.
C I
ER Interrupt
Here
F0 F0 F0
C I C 0 0 I
F1
Interrupt Here
C 0 0 I
Interrupt Here
F2
Save this interrupt
F3
Interrupt Here
Figure 7. The Interrupt Control of VT86C100A
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Preliminary VT86C100A
VT86C100A REGISTERS
Group 1 : Internal Command Status Register (CSR) Layout
NO 00 04 08 0c 10 14 18 1c 20 24 28 2c 30 34 38 3c 40 44 48 4c 50 54 58 5c 60 64 68 6c 70 74 78 7c byte3 PAR3/KEY3 TCR byte1 byte0 PAR1/KEY1 PAR0/KEY0 PAR5/KEY5 PAR4/KEY4 CR1 CR0 IMR2 IMR0 ISR1 ISR0 MAR3 MAR2 MAR1 MAR0 MAR7 MAR6 MAR5 MAR4 Curr Rx Desc Addr Curr Tx Desc Addr Current Rx Desc 0 Current Rx Desc 1 Current Rx Desc 2 Current Rx Desc 3 Next Rx Desc 0 Next Rx Desc 1 Next Rx Desc 2 Next Rx Desc 3 Current Tx Desc 0 Current Tx Desc 1 Current Tx Desc 2 Current Tx Desc 3 Next Tx Desc 0 Next Tx Desc 1 Next Tx Desc 2 Next Tx Desc 3 Current Rx DMA Pointer Current Tx DMA Pointer Tally counter test port BCR1 BCR0 MIISR PHY ADR MII DATA REG MIIADR MIICR GPIO TEST EECSR CFGD CFGC CFGB CFGA Tally counter_CRC Tally counter_MPA byte2 PAR2/KEY2 RCR type RW RW RW RW RW RW RW RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RW RW RW RW RW RW RW
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Preliminary VT86C100A
Configuration and Diagnostic Registers
Register Bit 7
EELOAD
Bit 6
JUMPE R TPACE N BROPT DIAG
Bit 5
MMIOE N MRDM DLYEN MRDL EN
Bit 4
MIIOPT TXARB IT DTSEL MAGIC
Bit 3
AUTO OPT RXARB IT BTSEL CRAD OM
Bit 2
MT10E NI MWW AIT BPS2 CAP
Bit 1
MT10E NO MRWA IT BPS1 MBA
Bit 0
MT10EOE LATMEM BPS0 BAKOPT
Read/ Write 78H 79H 7AH 7BH
Conf. B Conf. C Conf. D Note :
1. 2.
QPKTDIS RES GPIOEN
The shaded area denoted that those bits are also selective via external jumpers. All reserved bit must be zero.
No. 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 6CH 6DH 6EH
Name PAR0 PAR1 PAR2 PAR3 PAR4 PAR5 RCR TCR CR0 CR1
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 DA7 DA15 DA9 DA17 DA25 DA33 RRFT2 RTSF SRST
Bit 6 DA6 DA14 DA10 DA18 DA26 DA34 RFT1 RTFT1 RDMD RDMD1
Bit 5 DA5 DA13 DA11 DA19 DA27 DA35 RFT0 RTFT0 TDMD TDMD1
Bit 4 DA4 DA12 DA12 DA20 DA28 DA36 PROM TXON KEYPA G
Bit 3 DA3 DA11 DA13 DA21 DA29 DA37 AB OFST RXON DPOLL
Bit 2 DA2 DA10 DA14 DA22 DA30 DA38 AM LB1 STOP FDX
Bit 1 DA1 DA9 DA15 DA23 DA31 DA39 AR LB0 STRT ETEN
Bit 0 DA0 DA8 DA16 DA24 DA32 DA40 SEP INIT EREN
ISR0 ISR1 IMR0 IMR1 MAR0 MAR1 MAR2 MAR3 MAR4 MAR5 MAR6 MAR7 RDA0 RDA1 RDA2 RDA3 TDA0 TDA1 TDA2 TDA3 MPHY MIISR BCR0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
CNT KEYI CNTM KEYIM FB7 FB15 FB23 FB31 FB39 FB47 FB55 FB63 AB7 AB15 AB23 AB31 AB7 AB15 AB23 AB31 MPO1 GPIO1P OL
BE SRCI BEM SRCM FB6 FB14 FB22 FB30 FB38 FB46 FB54 FB62 AB6 AB14 AB22 AB30 AB6 AB14 AB22 AB30 MPO0 LEDPO L REQOP T
RU ABTI RUM ABTM FB5 FB13 FB21 FB29 FB37 FB45 FB53 FB61 AB5 AB13 AB21 AB29 AB5 AB13 AB21 AB29
MFDC CRFT2
TU NBFI TUM NBFM FB4 FB12 FB20 FB28 FB36 FB44 FB52 FB60 AB4 AB12 AB20 AB28 AB4 AB12 AB20 AB28 PHYAD 4 PHYOP T CRFT1
TXE PRAI TXEM PRAIM FB3 FB11 FB19 FB27 FB35 FB43 FB51 FB59 AB3 AB11 AB19 AB27 AB3 AB11 AB19 AB27 PHYAD 3 MIIERR CRFT0
RXE OVFI RXEM OVFM FB2 FB10 FB18 FB26 FB34 FB42 FB50 FB58 AB2 AB10 AB18 AB26 AB2 AB10 AB18 AB26 PHYAD 2 MRERR DMAL2
PTX ETI PTXM ETM FB1 FB9 FB17 FB25 FB33 FB41 FB49 FB57 AB1 AB9 AB17 AB25 AB1 AB9 AB17 AB25 PHYAD 1 LNKFL DMAL1
PRX ERI PRXM ERM FB0 FB8 FB16 FB24 FB32 FB40 FB48 FB56 AB0 AB8 AB16 AB24 AB0 AB8 AB16 AB24 PHYAD0 SPEED DMAL0
VIA Technologies, Inc.
Preliminary VT86C100A
6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH
BCR1 MIICR MIIAD
R/W R/W R/W
MAUT O
RCMD MSRCE N
CTSF WCMD MDON E
CTF1 MDPM MAD4
CTF0 MOUT MAD3
POT2 MDO MAD2
POT1 MDI MAD1
POT0 MDC MAD0
EECSR TEST
R/W R/W
EEPR HBDIS
EMBP FCOL
LOAD BKOFF
DPM TSTOV F
ECS TSTUD F
ECK TEST2
EDI TEST1
EDO TEST0
CFGA CFGB CFGC CFGD MPAC0 MPAC1 CRCC0 CRCC1
R/W R/W R/W R/W R/W R/W R/W R/W
EELOA D QPKTD IS GPIOE N CD7 CD15 CD7 CD15
JUMPE R TPACE N BROPT DIAG CD6 CD14 CD6 CD14
MMIOE N MRDM DLYEN MRDLE N CD5 CD13 CD5 CD13
MIIOPT TXARB IT DTSEL MAGIC CD4 CD12 CD4 CD12
AUTOO PT RXARB IT BTSEL CRADO M CD3 CD11 CD3 CD11
MT10E NO MWWA IT BPS2 CAP CD2 CD10 CD2 CD10
MT10E NO MRWAI T BPS1 MBA CD1 CD9 CD1 CD9
MT10EO E LATMEN BPS0 BAKOPT CD0 CD8 CD0 CD8
VIA Technologies, Inc.
Preliminary VT86C100A
1.1 Configure Register Layout Configuration Register A (0x78) 0 GPIO2OE MD3 GPIO2OE : Output enable of GPIO2 pin GPIO2O : Output to GPIO2 pin GPIO2I : GPIO2 input status AUTOOPT : enable receive event auto transmit descriptor polling MMIEN : Memory mapped IO enable, accept memory command JUMPER : Jumper mode to select PHY and operation mode EELOAD : Enable EEPROM embedded and direct programming
GPIO2
Configuration Register B (0x79) 0 LATMEN n/a LATMEN: Latency timer effect enable MRWAIT : Master read insert one wait state 2-2-2-2 MWWAIT: Master write insert one wait state 2-2-2-2 RXARBIT : the receiving FIFO DMA will be interleave to transmitting FIFO DMA after 32 double words transaction. TXARBIT : the transmitting FIFO DMA will be interleave to receiving FIFO DMA after 32 double words transaction. MRDM : Memory read multiple capable TPACEN : Tx descriptor pacing algorithm enable QPKTDIS : disable transmit frame queuing.
4
TXARBIT
n/a
7
QPKTDIS
n/a
Configuration Register C (0x7A) Bit Symbol Jumper 0-2 BPS0n/a BPS3
Function Boot PROM Select: Select size at which boot PROM begins and the size Bit2 Bit1 Bit0 Size 0 0 0 No Boot PROM 0 0 1 8K 0 1 0 16K 0 1 1 32K 1 X X 64K BTSEL : Bootrom timing select DLYEN : Delay transaction while memory read Bootrom BROPT : set Bootrom address line above Bootrom size selected to logic 1 for small size Bootrom
Configuration Register D (0x7B) 0 BAKOPT n/a BAKOPT : Back-off algorithm optional
VIA Technologies, Inc.
Preliminary VT86C100A
4
MAGIC
n/a
MBA : Modify back off algorithm CAP : Capture effect back off CRADOM : Random back off algorithm MAGIC : Turn on Magic key DIAG : GPIOEN : Turn on GPIO2 input status change monitor
7
GPIOEN
n/a
VIA Technologies, Inc.
Preliminary VT86C100A
VT86C100A Command Status Registers
MAC command and status register Group CR0: Command Register 0 (08H; Type=R/W) This register is used to select register pages, enable or disable remote DMA operation and issue commands.
Reserved This bit indicates that the VT86C100A receive poll demand enable This bit indicates that the VT86C100A transmit poll demand enable This bit indicates that the VT86C100A start transmit state while STRT bit on This bit indicates that the VT86C100A start receive state while STRT bit on This bit indicates that the VT86C100A into STOP state , this bit set by SFRST bit or hardware reset This bit indicates that VT86C100A enter the start command. Initialize Start : When set on the VT86C100A start to set its bus master register the start
6 5 4 3 2 1 0 CR1:
RDMD TDMD TXON RXON STOP STRT INIT
Command Register 1 (09H; Type=R/W) This register is used to select register pages, enable or disable remote DMA operation and issue commands.
This bit is set when VT86C100A enters reset state and is cleared when a start command is issued to the CR1. It is also set when receive buffer overflows or system error. Reserved Disable transmit auto polling This bit set MAC to full duplex in 10BaseT or 100BaseT mode Early transmit mode enable while CFGD[1] be enable, this bit be clear while hardware reset only Early receive mode enable while CFGD[0] be enable, this bit be clear while hardware reset only
6-4 3 2 1 0
RES DPOLL FDX ETEN EREN
RCR:
Receive Configuration Register (06H; Type=R/W) This register reflects the NIC receive configuration and reset by hardware reset and software reset Bit Symbol Description Receive store and forward 7 RRSF 6-5 RFT[1-0] Receive FIFO Threshold.
RRFT2 RRFT1 RRFT0 Threshold 0 0 0 64 bytes 0 0 1 32 0 1 0 128 0 1 1 256 1 0 0 512 1 0 1 768 1 1 0 1024 1 1 1 Receive store and forward If PRO=1, all packets with physical destination address are accepted. If PRO=0, physical address must match the node address programmed in PAR0-5 If AB=1, packets with broadcast destination address are accepted. If AM=0, packets with broadcast destination are rejected. If AM=1, packets with multicast destination address are accepted. If AM=0, packets with multicast destination are rejected.
4 3 2
PRO AB AM
VIA Technologies, Inc.
Preliminary VT86C100A
1 0
AR SEP
If AR=1, packets smaller than 64 bytes are accepted. If AR=0, packets smaller than 64 are rejected. If SEP=1, packets with receive errors are accepted. If SEP=0, packets with receive errors are rejected.
TCR: Transmit Configuration Registers (07H, Type=R/W) Bit Symbol Description Transmit and store and forward : till whole packet enter into FIFO then start transmit 7 RTSF 6-5 RFT[1-0] Transmit FIFO Threshold :
RTSF RTF1 RTF0 Threshold 0 0 0 64 bytes 0 0 1 32 0 1 0 128 0 1 1 256 1 0 0 512 1 0 1 768 1 1 0 1024 1 1 1 Transmit store and forward Reserve Back-off priority selection : change the back off algorithm as National specification Loopback mode select for transmit : 0 0 Normal 0 1 Internal loopback 1 0 ENDEC loopback for 10Base-T or MII loopback 1 1 223 loopback or others Reserved.
4 3 2-1
OFSET LB[1-0]
0
-
VIA Technologies, Inc.
Preliminary VT86C100A
ISR:
Interrupt Status Register (0CH; Type=R/W) This register reflects the NIC status. The host reads it to determine the cause of the interrupt Individual bits are cleared by writing a "1" to the corresponding bit. It must be cleared after power up.
Magic packet key received interrupt status Port status change interrupt status transmit abort interrupt status, this bit will be set while excessive collision No more receive buffer to use FIFO overflow condition, next packet race into FIFO with current packet receiving FIFO overflow interrupt status Transmit descriptor underflow while in early transmit mode or general I/O pin M10TENI status change interrupt while GPIOEN=1, this interrupt can be used as PHY report the link status change. Indicates the received packet has filled the first data buffer. CRC error or packet race tally counter overflow interrupt, software can maintain drivers CRC error counter above 32 bit PCI Bus error interrupt Receive buffer unavailable Transmit buffer underflow Transmit error bit is set when a packet transmission is aborted due to excessive collisions. This bit is set when a packet is received with one or more of the following errors: 1) CRC error, 2) Frame alignment error and 3) Missed packet. This bit indicates that packet is transmitted with no errors. This bit indicates that packet is received with no errors.
IMR
Interrupt Mask Register (0EH; Type=R/W ) All bits correspond to the bits in the ISR register. Power up=all 0s. Setting individual bits will enable the corresponding interrupts.
EEPROM Configuration and status Register Group EECSR EEPROM Command Status Register (74H, Type=R/W)
EEPROM programming status EEPROM embedded program enable, the VT86C100A will set this bit to zero after programming complete. Dynamic reload EEPROM content, the PAR[5-0] will be update Direct program EEPROM EEPROM interface chip select status EEPROM interface clock status EEPROM interface data in status EEPROM interface data out status
6 5 4 3 2 1 0
EMBP LOAD DPM ECS ECK EDI EDO
VIA Technologies, Inc.
Preliminary VT86C100A
MII port control and status Register Group MIICR MII interface control register (070H, Type=R/W)
MII management port auto polling enable, MIICR has no effect while this set on read enable to read PHY status, reset while complete and PHY status will be store in register MII data register 0x72 write enable to program PHY, reset while PHY programmed completely direct program mode enable, while MDPM be set , the WCMD and RCMD have no effect MDIO output enable indicator while direct program mode MII interface management port data output status MII interface management port data input status MII interface management port clock status
6 5 4 3 2 1 0
RCMD WCMD MDPM MOUT MDO MDI MDC
MIIAD MII CSR offset address register (071H, Type=R/W)
MSRCE N 5 MDONE MII management port address bit 4 4 MAD4 MII management port address bit 3 3 MAD3 MII management port address bit 2 2 MAD2 MII management port address bit 1 1 MAD1 MII management port address bit 0 0 MAD0 The MII management port address default value be (00001)b, MIISR MII status register (06dH, Type=R/W)
GPIO1POL : General purpose I/O 1 pin output polarity, when this bit set as '1', the GPIO1 pin output active high; set as '0', the GPIO1 pin output active low. Reserve MFDC : Accelerate the MDC speed when VT86C100A enter MII auto polling; MFDC set as '0', MDC be normal speed; or MFDC set as '1' , MDC be 4 times speed. PHYOPT : set 1 use default external PHY device address as 0001 MIIERR : PHY device coding error by insert RX_ERR, write to clear it. MRERR : MII Management read error, write to clear it LNKFL : Link fail in 10 or 100MHz SPEED : Network speed, 0 as 100MHZ, 1 as 10MHz
6
6 5 4 3 2 1 0
res MFDC PHYOPT MIIERR MRERR LNKFL SPEED
PHYADR MII configuration register (06cH, Type=R/W)
VIA Technologies, Inc.
Preliminary VT86C100A
MII management port polling timer interval, timer unit be MDC clock cycle MPO1 MPO0 clock 0 0 1024 0 1 512 1 0 128 1 1 64
5 4-0
res PHYAD[ 4-0]
PHY[4-0] : external PHY device address , these register bytes stored from EEPROM loading when power up or EEPROM auto-reloading or can be programmed by software, default as (00001)b
VIA Technologies, Inc.
Preliminary VT86C100A
[This page left to blank]
VIA Technologies, Inc.
Preliminary VT86C100A
R6 0 R7 0 R8 0 MA[15:0] MA[15:0] 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 AD25 -CBE3 AD23 AD22 AD20 AD19 AD17 -FRAME -TRDY -STOP -PERR PAR AD15 AD13 AD11 AD9 -CBE0 JP1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 AD24 IDSEL AD21 AD18 AD16 -CBE2 -IRDY -DEVSEL -CBE1 AD14 AD12 AD10 AD8 AD7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
R3 0 CB8 22UF CB7 22UF CB5 22UF CB4 22UF CB3 22UF CB2 22UF CB1 22UF R4 0 R5 0
PCIVCC
MD[7:0]
MD[7:0]
P2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
P1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 PCI_CONA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -CBE3 -CBE2 -CBE1 -CBE0 IDSEL -FRAME -IRDY -TRDY -DEVSEL -STOP PAR PCICLK -INTA -PCIRST -GNT -REQ -PERR -PME 121 122 123 124 127 128 1 2 5 7 8 9 11 12 13 14 27 28 29 30 31 32 35 36 38 39 40 42 43 44 45 46 3 16 26 37 4 17 18 19 20 21 25 115 113 114 118 119 23 120 10 22 34 47 56 65 76 87 97 108 117 125
U1 VT3043E AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 CBE3 CBE2 CBE1 CBE0 IDSEL FRAME IRDY TRDY DEVSEL STOP PAR PCICLK INTA PCIRST GNT REQ PERR PME VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD MCRS MCOL MTXD3 MTXD2 MTXD1 MTXD0 MTXE MTXC MERR MRXC MRXDV MRXD0 MRXD1 MRXD2 MRXD3 MDC MDIO M10TEN PRTENL PRTENH MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MD7 MD6 MD5 MD4 MD3 MD2/EECK MD1/EEDI MD0/EEDO EECS BPRD TST NC2 NC HDRST SVDD SVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 90 91 92 93 94 95 96 99 100 101 102 103 104 105 106 109 110 112 61 62 84 83 82 81 80 79 78 73 72 71 70 69 68 67 64 63 60 59 58 55 54 53 52 51 49 50 89 86 85 111 74 75 MCRS MCOL MTXD3 MTXD2 MTXD1 MTXD0 MTXEN MTXCK MRXER MRDCK MRXDV MRXD0 MRXD1 MRXD2 MRXD3 MDC MDIO M10TEN PRTENL PRTENH MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 EECS -BPRD TST NC2 NC HDRST SVDD C10 .O1u SVSS C9 10uF EECS -BPRD TST NC2 NC HDRST R2 3.6 0805 C8 .1u MCRS MCOL MTXD3 MTXD2 MTXD1 MTXD0 MTXEN MTXCK MRXER MRXCK MRXDV MRXD0 MRXD1 MRXD2 MRXD3 MDC MDIO M10TEN PRTENL PRTENH
PCIVCC
PCIVCC -INTA
-PRSNT1 -PRSNT2
PCICLK -REQ PCIVCC AD31 AD29 AD27 AD25 -CBE3 AD23 AD21 AD19 AD17 -CBE2 -IRDY -DEVSEL -PERR
-PCIRST PCIVCC -GNT AD30 AD28 AD26 AD24 IDSEL AD22 AD20 AD18 AD16 -FRAME -TRDY -STOP
-PCIRST
-PME R1 0
39 41 43 45 47 49 51 53 55 57 59 61 63
AD6 AD3 AD1 EECS MD0 MD2 MD4 MD6 PRTENL MA0
AD5 AD4 AD2 AD0 -BPRD MD1 MD3 MD5 MD7 PRTENH MA1
40 42 44 46 48 50 52 54 56 58 60 62 64
-CBE1 AD14 AD12 AD10
PAR AD15 AD13 AD11 AD9 -CBE0 AD6 AD4 AD2 AD0 PCIVCC -PME C1 C2 C3 C4 C5 C6 C7 C12 C13 C11 C14 C15 .1u .1u .1u .1u .1u .1u .1u .1u .1u .1u .1u .1u
65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101
MA2 MA4 MA6 MA8 SVSS MA10 MA12 MA14 NC TST MCOL MTXD2 MTXD0 MTXCK MRXCK
MA3 MA5 MA7 SVDD MA9 MA11 MA13 MA15 NC2 MCRS MTXD3 MTXD1 MTXEN MRXER MRXDV
66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102
AD8 AD7 AD5 AD3 AD1 PCIVCC
PCI_CONB
103 105 107 109 111 113 115 117 119 121 123 125 127
MRXD0 MRXD2 MDC HDRST -INTA PCICLK -REQ AD31 AD29 AD27
MRXD1 MRXD3 MDIO M10TEN -PCIRST -GNT -PME AD30 AD28 AD26
104 106 108 110 112 114 116 118 120 122 124 126 128
6 15 24 33 41 48 57 66 77 88 98 107 116 126 |LINK |2.SCH |3.SCH Title Size C Date:
HEADER 72X2
VIA TECHNOLOGIES, INC.
VT3043E Bench Board Document Number VT5134A Thursday, September 04, 1997 Sheet 1 of 3 Rev A
VIA Technologies, Inc.
Preliminary VT86C100A
R78 510 RN2 510 1 3 5 7 2 4 6 8 R52 510 TXO+/TXU+ TXUTXOC37 .1u C38 .1u RXI+ RXIU2 26 23 13 15 16 25 24 20 21 12 P0 R32 *0 19 17 18 14 22 VCC EXTVCC VCC PMRD+ PMRDPMID+ PMIDSD+ SDENCSEL LBEN EQSEL /CDET GND GND DP83223 Transceiver TXREF 6 R14 *2K 1 RXGND RXGND TXVCC TXVCC RXVCC RXVCC TXO+ TXORXI+ RXITXGND TXGND 5 11 4 27 9 8 2 1 7 10 3 28 R79 0/75 C34 .1u TXO+/TXU+ TXOR17 10/0 R18 10/0 R19 39/49.9 3 3 C39 .1u 2 2N3904 1 Q3 R36 510 2 2N3904 Q2 3 R20 39/49.9 RXI+ RXIR38 47.5 C43 *10p R39 47.5 R53 510
D9 PWR U3 82 75 76 77 78 TX_ER MII_CRS R54 33 R55 33 74 73 66 65 55 56 57 58 33 62 64 63 43 72 67 RESET REFIN CLK25 OSCIN 44 86 81 2 34 33 96 39 51 70 97 40 52 71 59 68 79 84 60 61 69 80 85 R22 75 OSCIN C17 10P R24 *75 18 22 31 32 19 27 30 35 ANAVCC 12 15 9 87 3 11 10 88 TX_CLK TXD3 TXD2 TXD1 TXD0 TX_EN TX_ER CRS_P2 COL RXD3 RXD2 RXD1 RXD0 RX_CLK RX_DV RX_ER_P4 RX_EN MDC MDIO RESET REFIN CLK25M OSCIN X2 X1 VCC_A VCC_A VCC_A PCSVCC_A GND_A GND_A GND_A PCSGND_A VCC_B VCC_B VCC_B REFVCC_B GND_B RCLKGND_B GND_B GND_B REFGND_B RXVCC_C TDVCC_C PLLVCC_C OVCC_C RXGND_C TDGND_C PLLGND_C OGND_C CRMVCC_D ECLVCC_D ANAVCC_D CGMVCC_D OSCGND_D CRMGND_D ANAGND_D CGMGND_D DP83840A Physical Layer 1 SD+ SDENCSEL_P1 LBEN_P0 LED_TX LED_RX LED_LK LED_P/F LED_COL SPEED_10 TXU+ TXUTXS+ TXSRXI+ RXIREQ RTX TD+ TDRD+ RD42 41 38 37 36 54 26 25 24 23 21 20 29 28 17 16 5 6 8 7 53 49 P1 PUD01 R81 20 R82 22 SPEED10 R12 R13 R15 R16 10 10 *0 *0 D1 D2 D3 D4 D5 D6 TX RX LK P/F COL 100
R48 33 MTXCK MTXD3 MTXD2 MTXD1 MTXD0 MTXEN MCRS MCOL MRXD3 MRXD2 MRXD1 MRXD0 MRXCK MRXDV MRXER MDC MDIO
R35 0 R11 0 R40 *49.9 1% R41 *49.9 1%
R49 MII_RXER R10 MDC MDIO 4.7K
PTD+ PTDPRD+ PRDPSD+ PSD-
R80 0/75
1%
1% 1 3 5 7
RN1 510 2 4 6 8
R21
4.7K
P3/100
NS 840 R42 R22 R23 R24 OSC2 V V 50M
MTD972 V V 25M
AN0 AN1 REPEATER
95 46 47
AN0 AN1 R63 4.7K
SPEED10
R33 0
2 2N3904 1 Q1
10BTSER BPALIGN BP4B5B BPSCR J_TD0 J_TDI J_TRST J_TCLK J_TMS PHYAD3 NC NC NC RES_0 RES_0 RES_0 RES_0
98 99 100 1 50 91 92 93 94 89 13 14 83 4 45 48 90
R25 510 RXI+ PUD02 RXIR9 10K P3/100 TXOPUD03 R42 *10K C41 *.1u C48 39p L4 FB C47 39p C35 .1u R31 10 15 R37 *0 TXO+/TXU+ TXUL3 FB 2 3 16 14 1
J1 RJ-45 L1 RD+ RX+ CT CT TD+ RXTX+ CM 7 5 6 10 12 14 13 12 11 10 9 11 TDPT4171 TXR27 75 R30 75 R29 75 R28 75 FGND TX_ER CX1 .1u 1 2 3 4 5 6 7 8
OSC1 1 2 NC GND VCC OUT 4 3
50MHz/*25MHz
REFIN U4A -PCIRST 1 74LS14 HDRST R51 33 R23 0 2
CLK25
R26 4.7K
R50 33 RESET
R56 0 R57 *0
PUD01 RP2 130 2 3 4 5 6 7 PRD+ PRDPSDPSD+ PTDPTD+ 2 3 4 5 6 7 RP1 82 1 P1 R59 10K P0 R58 10K 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 AN0 PHY0 1 2 3 AN0 PUD03
R44 R43
*4.7K *4.7K
PUD01 PHY1 AN1 1 2 3 AN1 PUD02 PUD03 PHY2
R47 R45 R46
*4.7K *4.7K *4.7K
L2 47uH C40 22u ANAVCC C16 .001u
C18 .1u
C19 .1u
C20 .1u
C21 .1u
C22 .1u
C23 .1u
C42 .1u
C24 .1u
C25 .1u
MII_CRS *Use RP1,RP2 or Only RP2 -> 510 P3/100 C32 .1u C33 .1u C26 .1u C27 .1u C28 .1u C29 .1u C30 .1u C31 .1u MII_RXER
R60 10K R61 10K R62 10K
PHY3
'*' for Myson PHY and Transceiver VIA TECHNOLOGIES, INC.
PHY4
Title NS or Myson's PHY & Transceiver Size C Date: Document Number VT5134A Thursday, September 04, 1997 Sheet 2 of 3 Rev A
VIA Technologies, Inc.
J4 EECS -BPRD M10TEN PRTENH PRTENL TST NC2 NC EECS -BPRD 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 2 3 4 5 6 7 8 9 10K RP4 1 J5 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 4.7K RP6 1 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0
Preliminary VT86C100A
J2 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 2 3 4 5 6 7 8 9 4.7K RP5 1 J3 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 10K RP3 1
TP1 PCI_PWR 1 D7 1N4148 MD[7:0]
D8 1N4148 1
TP2 U8A 2 3 U8B 4 PCI_GOOD 1
MD[7:0]
74HC14 R76 4.7K
74HC14
MA[15:0]
MA[15:0] R75 100K U8D 8 9 6 U8C 5 C44 100p 2 3 Q4 NPN ISOLATE 1 1 R74 10K VCC SENSE RESET RESET 8 7 6 5 R71 10K ALTRST 1 R72 7.8K TP3
74HC14 U5 MD1 MD2 EECS 3 2 1 DI SK CS 93C46 DO VCC GND 4 8 5 MD0 C46 .1u C45 .1u R77 0 1 2 3 4 U7 REF RESIN CT GND
74HC14
R73 10K TP4
TL7705A
TP5 AUX_PWR U6 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 20 22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE 27512 VIA TECHNOLOGIES, INC. O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 1 P3 R68 0 -PME 1 2 3 4 5 6 AUX5V NC GND WAKUP GND AUX5V AUX5V_CON R69 0 R70 0
R66 4.7K R64 0 MA14 MA15 R65 0
R67 4.7K
-BPRD
Title VT3043E Strapping Size C Date: Document Number VT5134A Thursday, September 04, 1997 Sheet 3 of 3 Rev A

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